1. Field of the Invention
The invention relates to accelerated graphics port (AGP) devices, and more specifically, to a method and apparatus for eliminating bus contention on an AGP device.
2. Description of Related Art
The rapid growth in popularity of graphical computer operating systems, such as Microsoft Windows, has resulted in a tremendous increase in the amount of information that must be moved between a computer's processor, memory, video and hard disks. Information is transmitted between various computer system components over a bus. A bus is like a highway on which data travel within a computer. A bus normally has access points, or places into which a device can tap to become attached to the bus, and devices on the bus can send to, and receive information from, other devices. Further, computer systems typically have multiple buses. For example, the processor bus is used to transfer information between the CPU, or processor, and system memory, and an I/O bus is used for communication among devices such as video cards, disk storage devices, networks, mice, modems, etc., and the CPU and memory. The industry standard architecture (ISA) bus was commonly used as the I/O bus in early personal computer (PC) systems.
The transformation of the software world from text to graphics also resulted in much larger programs and more storage requirements. A complete screen of monochrome text is just 2,000 bytes of information. A standard 256-color Windows screen requires over 300,000 bytes, an increase of about 15,000%. From an I/O bus standpoint, much more I/O bandwidth is needed to handle the additional data going to and from the video card and the increasingly larger and faster hard disks. Further, CPU performance continues to increase in a similar manner, additionally increasing the demands for transmitting information over the bus.
The ISA bus, still running at the same speed and bus width that it did on the IBM AT, was finally and totally overcome by these increasing demands and became a major bottleneck to improving system performance. Increasing the speed of the processor accomplished little if it was always waiting for the slow I/O bus to transmit data. Thus, a faster bus that would augment the ISA bus and be used especially for high-bandwidth devices such as video cards was developed. This new bus was put on (or near) the much faster processor bus, to let it run at or near the external speed of the processor, and to allow data to flow between these devices and the processor without having to go through the much slower ISA bus. By placing these devices "local" to the processor, the local bus. was born.
The first local bus to gain popularity was the Video Electronics Standards Association (VESA) local bus. The VESA local bus was developed primarily to improve video performance in PCs. The VESA bus is a 32-bit bus, which is in a way a direct extension of the processor bus with which it was implemented. The VESA bus has largely been replaced by the peripheral component interconnect (PCI) bus. The PCI bus is described in detail in the PCI Local Bus Specification, revision 2.1, available from the PCI Special Interest Group, Hillsboro, Oregon. The PCI Local Bus Specification is incorporated by reference herein in its entirety.
The PCI bus can transfer information in a burst mode, wherein after an initial address is provided, multiple sets of data can be transmitted sequentially. On a bus such as the PCI bus, a great deal of information flows through the bus every second. Normally, the processor is required to control the transfer of this information. To improve performance, some devices on the bus have the ability to take control of the bus and do the work themselves. Devices that can do this are called bus masters.
FIG. 1 illustrates a prior art computer system 10 employing a PCI local bus 12. The system includes a system CPU 14 coupled to a chipset 16. The chipset 16 is coupled to the system memory 18 and the PCI bus 12. A graphics accelerator 20 is coupled to a video memory 22 and the PCI bus 12. The graphics accelerator 20 is coupled to a display device 24. A plurality of I/O devices 25, such as disk storage devices, audio systems, network interfaces, etc., are further coupled to the PCI bus 12.
The graphics accelerator 20 may be installed directly on a motherboard, in which case it is known as an "on board" or "video down" graphics accelerator. Alternatively, the graphics accelerator 20 may be installed as a component on a separate circuit card assembly that is seated in a connector coupled to the PCI bus 12, referred to as an "addin" video card. The video down graphics solution is desirable, since it is typically cheaper than an add-in card. A single chip is involved rather than an entire circuit card assembly. If the user desires to upgrade a video down graphics accelerator to a higher performance graphics accelerator chip, however, an add-in card is required.
As shown in FIG. 1, the video system "shares" the PCI bus with several other I/O devices. Computer video has increased in complexity with developments in areas such as 3D acceleration and full-motion video playback Hence, the amount of information transferred between the graphics accelerator and the system chipset has greatly increased, placing greater demands on the PCI bus. To prevent saturation of the PCI bus with video information, a new information interface was developed known as an accelerated graphics port (AGP). The AGP is based on a set of performance extensions or enhancements to the PCI bus. AGP is discussed further in the Accelerated Graphics Port Interface Specification, revision 1.0, dated Jul. 31, 1996, available from Intel Corp., which is hereby incorporated by reference in its entirety.
FIG. 2 illustrates a prior art computer system 11 including an AGP 26. In addition to providing an AGP on the system motherboard, the graphics accelerator 21 must be AGP-compliant, and the chipset 16 must include an AGP controller. The configuration of the computer system 11 is essentially identical to the computer system 10 illustrated in FIG. 1, except the AGP graphics accelerator 21 is not coupled to the PCI bus 12. Rather, the AGP 26 connects the AGP graphics accelerator 21 to the chipset/AGP controller 17.
The AGP 21 provides a dedicated, high-speed data connection directly between the chipset 17 and the graphics accelerator 21, and also frees the video traffic from the constraints of the PCI bus 12.
As discussed above, a video down graphics accelerator is often desirable from a cost standpoint. An onboard PCI graphics accelerator can be upgraded simply by seating a PCI graphics accelerator add-in card in a PCI expansion slot. The PCI bus 12 is designed to provide data transfer among several devices. At boot-up, each device 25 on the PCI bus is configured. Thus, an ID select (IDSEL) is assigned to each device 25 on the PCI bus 12 to identify the target of a configuration transaction. During configuration transactions, each device 25 on the PCI bus 12 samples its IDSEL during each PCI bus transaction to determine whether it is the target of the configuration transaction.
The AGP 26 is patterned after the PCI bus 12. As illustrated in FIG. 2, however, the AGP 26 connects only two devices, rather than providing a transmission path for several devices. Thus, the AGP 26 is referred to as a "port" rather than a "bus," since it provides a "point to point" connection. To this end, the AGP 26 and AGP compliant devices are configured such that only two devices, the AGP graphics accelerator 21 and the system chipset 17, may be coupled to the AGP. The IDSEL is internally connected to a preselected address line, since there is no requirement to identify the target of a configuration transaction. This creates a problem when a computer user desires to upgrade from an onboard, or video down, AGP graphics accelerator 21 to another AGP graphics accelerator. If an additional AGP graphics accelerator is coupled to the AGP 26 (via an add-in card connector), both AGP graphics accelerators will contend for the AGP 26, attempting to simultaneously respond to AGP cycles, locking the AGP 26.
With existing AGP implementations, the only way to upgrade to an improved AGP graphics accelerator is to replace the entire motherboard or attempt to desolder the existing chip from the motherboard and solder in a new chip. Neither solution is practical. This is confirmed by revision 1.0 of the AGP specification (July 1996), which states, "[T]he AGP video solution can be implemented either integrated as video down on the motherboard, or as an AGP expansion slot, but both cannot be supported simultaneously."
Thus, a need exists for a device and method for eliminating contention for an AGP among multiple AGP devices.